1. Field of the Invention
The present invention relates to oscillators for use in, for example, communication apparatuses for performing wired or wireless communication.
2. Description of the Related Art
There are known oscillators for use in, for example, communication apparatuses for performing wired or wireless communication.
Referring to FIG. 3, a specific example of such an oscillator will be described.
An oscillator B, which is an example of a known oscillator, has a known phase locked loop (PLL) configuration. The oscillator B is controlled by receiving, by a controller 150 included therein, a latch signal (LE), a data signal (DATA), and a clock signal (CLK), which are output from a micro processing unit (MPU) 100.
Specifically, the oscillator B includes a phase frequency detector (PFD) 130, a charge pump (CP) 140, a loop filter (LF) 300, and a voltage-controlled oscillator 400. The phase frequency detector 130 obtains a reference signal that is externally adjusted with high accuracy so as to serve as a reference for obtaining an output signal at a desired frequency from an RF output terminal 170 (hereinafter simply referred to as “REF”) and an output signal that is actually output by the oscillator B (hereinafter simply referred to as “RF”), detects the phase difference between the obtained REF and RF, and, on the basis of the detection result, outputs a control command signal for controlling the output signal to achieve the desired frequency. The charge pump 140 processes, such as inverts or non-inverts, the control command signal output from the phase frequency detector 130 in accordance with the phase difference. The loop filter 300 smoothes the control command signal output from the charge pump 140. The voltage-controlled oscillator 400 generates RF (output signal) at the desired frequency on the basis of the smoothed control command signal generated by the loop filter 300.
The RF is output from the RF output terminal 170, and the REF is input from an REF input terminal 160.
The REF and RF are signals applied to the phase frequency detector 130. These two signals are divided in advance by a frequency divider 110 (for RF) and a frequency divider 120 (for REF) for dividing the corresponding signals by predetermined division ratios, respectively, prior to being input to the phase frequency detector 130. When the REF and RF have the same cycle, the frequency dividers 110 and 120 need not be provided.
Since the charge pump 140 converts the output signal of the phase frequency detector 130 into three modes, namely, a positive constant current output, a negative constant current output, and no output (off), in accordance with the phase difference between the input signals, the charge pump 140 may be omitted.
A frequency synthesizer IC is an example of an IC chip having the frequency dividers 110 and 120, the phase frequency detector 130, the charge pump 140, and the controller 150, which are packed in one integrated circuit.
The oscillator B arranged as described above obtains and generates these signals with, for example, timing shown in FIG. 4.
For example, the REF input from the REF input terminal 160 is divided by the frequency divider 120 (in this case, the division ratio R=2) to become FR1. At the same time, the RF output from the voltage-controlled oscillator 400 is divided by the frequency divider 110 (in this case, the division ratio R=8) to become FN1. The two signals (FR1 and FN1) now have the same cycle and are obtained by the phase frequency detector 130.
The phase frequency detector 130 detects the phase difference between the obtained two signals (FR1 and FN1) and outputs a control command signal based on the phase difference.
The charge pump 140 processes the output control command signal on the basis of the control command signal to generate a processed signal CP1. This processed signal CP1 is smoothed by the loop filter 300 and, on the basis of the smoothed signal, the voltage-controlled oscillator 400 outputs RF at the desired frequency.
The processing of the control command signal by the charge pump 140 will now be described.
For example, referring to FIG. 4, when the phase of the FR1 is ahead of the phase of the FN1, the charge pump 140 outputs the CP1 as a positive constant current pulse with a pulse width corresponding to the phase difference. On the other hand, referring to FIG. 5, when the phase of the FR1 is behind the phase of the FN1, the charge pump 140 outputs the CP1 as a negative constant current pulse with a pulse width corresponding to the phase difference. During a no-pulse period, the output of the charge pump 140 is opened.
The voltage-controlled oscillator 400 controls RF to achieve the desired frequency value in accordance with the polarity and the pulse width of the constant current pulse serving as the CP1.
In wired or wireless communication environment that has been developing greatly in recent years, advanced digital modulation schemes have been increasingly used at higher frequencies.
There is a demand for reducing, as much as possible, phase noise generated in the oscillator B, which is used to convert the frequency of a digitally-modulated signal at the time the digitally-modulated signal is demodulated.
It is known that the greater the division ratios of the frequency dividers 110 and 120, the greater the phase noise generated in the oscillator B.
A specific experiment was conducted in which the RF output frequency was 6 GHz, the division ratio N=200, and the processing frequency of the phase frequency detector 130 was 30 MHz. The result of this experiment shows that the floor level of phase noise is approximately −97 dB/Hz (the floor level designates a low frequency component of the phase noise, when viewed from the upper limit value of the RF output frequency, that is, the level of phase noise primarily generated from the frequency synthesizer IC).
In contrast, another experiment was conducted in which the RF output frequency was 6 GHz, the division ratio N=6000, and the processing frequency of the phase frequency detector 130 was 1 MHz. The result of this experiment shows that the floor level of phase noise is approximately −84 dB/Hz.
The results of the experiments show that, given the same RF value, the greater the division ratio, the greater the phase noise.
To reduce the phase noise, the division ratio of each frequency divider may be reduced. At present, the phase frequency detector 130 has an upper limit of approximately 56 MHz for the phase comparison frequency. When the phase frequency detector 130 handles high frequencies, as described above, the frequency dividers with large division ratios must be used. Suppression of phase noise is thus difficult to achieve.
Japanese Unexamined Patent Application Publication No. 2001-144607 describes a technique of selectively using a digital phase detector with a PLL having a wide locking range and an analog phase detector with low phase noise, depending on whether the PLL is unlocked or locked. According to this technique, a low-phase-noise signal can be generated under a wide locking range. However, this technique requires the high-accuracy phase detectors that can achieve target phase noise.